MYK-41 DES ASIC
Downlink Encryptor/Decryptor
A radiation-hardened VLSI chip for embedment applications, the MYK-41 VLSI encrypts or decrypts using the DES algorithm.
Features and Benefits
- Cryptographically compatible with DES FIPS Pub 46.
- Operates in Electronic Codebook (ECB) or Output Feedback (OFB) mode.
- Off-the-shelf QML "Q" availability.
- Binary TTL data format.
- Maximum data rate of 160 Mbps with system clock at 20 MHz.
- Subject to export controls.
- Meets QML Class Q requirements of MIL-PRF-38535.
- DESC-qualified JAN CMOS gate array manufacturer.
- Radiation hardened for space applications.
Specifications
- Package: 172-pin ceramic flat pack
- Data Rate: 1bps to 160Mbps
- Operating Voltage: 4.5 to 5.5 VDC
- Power Consumption: 40 mW/MHz (nominal)
- Data Interface: I/O--32-bit parallel TTL, Clocks--CMOS
- Format: NRZ-L
- Processing: DESC-qualified JAN CMOS gate array
- Testing: Functional and propagation delays; Group E and DPA available.
- Temperature Range: -55 to +125° C
- Technology: Sub-micron CMOS
- Package: 172-pin ceramic flat pack
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