SafeXcel IP AES Accelerators

The SafeXcel IP AES Accelerators are designed to meet the unique requirements of semiconductor manufacturers and provide unmatched reliability, fast integration, low gate count, cost-effectiveness, and maximum performance. Part of SafeNet's broad IP design product portfolio, the SafeXcel IP AES Accelerators are typically deployed in processors used in networking and storage appliances that require hardware acceleration for strong cryptography-based security. The SafeXcel IP AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Benefits

• Silicon-proven AES solution
• Fast & easy to integrate
• Flexible, layered design
• Maximum performance
• Low gate count
• Includes feedback mode logic
• Includes key scheduling logic
• World-class support

Features

• Supported key sizes: 128, 192, 256 bits
• Includes feedback mode logic. Supports Electronic Code Book (ECB), Cipher Block Chaining (CBC), 128-bit Output Feedback (OFB), 1-bit, 8-bit, and 128-bit Cipher Feedback (CFB), and Counter (CTR)
• Fully synchronous design
• Includes key scheduling hardware

Deliverables

• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation script
• Synthesis script
• User's Manual with technical specifications, including the programmer's interface
• Developer's Manual with step-by-step descriptions that allows developers to easily install, verify, and synthesize the design