SafeXcel IP AES/GCM/XTS Accelerators

Even though the Advanced Encryption Standard (AES) algorithm was designed to allow high-speed implementations, its regular feedback modes such as CBC, CFB, and OFB are not ideal for supporting very high-speed networking applications. The AES-GCM and AES-XTS algorithms do not use these regular AES feedback modes and allow very high-speed encryption and authentication by enabling an implementation to make use of parallelism. Typical uses cases for AES-GCM and AES-XTS are high-speed transmission (virtual private networking) and disk storage (protection of data at rest). For transmission protection, AES-GCM can for instance implement authenticated encryption at the network layer (IPsec) or at the data link layer (IEEE 802.1ae).

As part of SafeNet’s award-winning silicon Intellectual Property (IP) product portfolio, the SafeXcel IP AES/GCM/XTS Accelerators are specifically suited for next generation processors deployed in networking and storage appliances that need to support combinations of AES (with its regular feedback modes), AES-GCM, and AES-XTS. The SafeXcel IP AES/GCM/XTS Accelerators do not only meet vendor requirements for very high throughputs, but also for fast integration and cost-effectiveness.

AES-GCM and AES-XTS Acceleration

The AES-GCM (Galois Counter Mode) has, since its publication in 2005, been used in many IPsec and MACsec (IEEE 802.1ae) applications. It is a very efficient algorithm, capable of running at high performance. AES-XTS has been adopted by IEEE P1619 for protection of data at rest.

Benefits

• Complete HW/SW system
• High-speed AES-XTS / AES-GCM solution
• Silicon-proven implementation
• Fast and easy to integrate into SoCs
• Flexible layered design
• Complete range of configurations
• World-class technical support

Features

• Supported key sizes: 128, 192, and 256 bits.
• Includes feedback mode logic.
• Various configurations available, with support for:
  • Electronic Code Book (ECB), Cipher Block Chaining (CBC), 128-bit Output Feedback (OFB), 1-bit, 8-bit, and 128-bit Cipher Feedback (CFB), Counter (CTR).
  • AES Galois Counter Mode (AES-GCM), using AES-CTR mode and GHASH.
  • Basic GHASH.
  • Liskov Rivest Wagner AES (AES-XTS).
  • AES-XTS (XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS))
• Fully synchronous design.
• Includes key scheduling hardware

Deliverables

• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation script
• Synthesis script
• User’s Manual with technical specifications, including the programmer’s interface
• Developer’s Manual with step-by-step descriptions that allows developers to easily install, verify, and synthesize the design