SafeXcel IP DES/3DES Accelerators

Designed for fast integration, low gate count, and maximum performance, the SafeXcel IP DES/3DES Accelerators address the unique needs of semiconductor OEMs and provide a reliable and cost-effective DES/3DES IP solution that is easy to integrate into SoC designs.

Part of SafeNet's extensive IP design portfolio, the SafeXcel IP DES/3DES Accelerators are typically deployed in semiconductors for next-generation applications that require cryptography-based security, including secure data communications, secure electronic transactions, and secure data storage.

Benefits

• Silicon-proven DES/3DES solution
• Fast & easy to integrate
• Flexible, layered design
• Maximum performance
• Low gate count
• Includes feedback mode logic
• Includes key scheduling logic
• World-class support

Features

• Supported key sizes: 64 (DES) and 192 bits (3DES)
• Includes feedback mode logic.
• Supports Electronic Code Book (ECB), Cipher Block Chaining (CBC), 1-bit, 8-bit, and 64-bit Output Feedback (OFB), 1-bit, 8-bit, and 64-bit Cipher Feedback (CFB).
• Fully synchronous design

Deliverables

• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation script
• Synthesis script
• User’s Manual with technical specifications, including the programmer’s interface
• Developer’s Manual with step-by-step descriptions that allows developers to easily install, verify, and synthesize the design