SafeXcel IP - MD5 and SHA Accelerators

Semiconductor designers require ready-to-use hardware implementations of the Message Digest algorithm 5 (MD5) and the Secure Hash Algorithm (SHA) that are silicon-proven and reliable, yet flexible to accommodate a wide variety of design goals. Part of SafeNet's award-winning IP product portfolio, SafeNet provides the SafeXcel IP MD5/SHA Accelerators to meet these requirements. Designed for fast integration, low gate count, and maximum performance, they address the unique needs of semiconductor OEMs and provide a reliable and cost-effective IP solution that is easy to integrate into SoC designs.

Applications

The SafeXcel IP MD5/SHA Accelerators are typically deployed in semiconductors for next-generation applications such as secure data communications, secure electronic transactions, and secure data storage. The hash algorithms are, for example, used for creation and validation of digital signatures, data integrity checking, password verification, key confirmation in key establishment protocols, time stamping, public-key infrastructure, and message authentication codes implementations such as HMAC. HMAC functionality is an optional function of the MD5/SHA Accelerator IP cores.

Standards compliance

The SafeXcel IP MD5/SHA Accelerators implement the MD5 algorithm, as specified in RFC 1321, and the Secure Hash Algorithms, as specified in FIPS (Federal Information Processing Standard) Publication 180-2. The accelerators include I/O registers, hash calculation cores, message padding logic, and data scheduling logic.

Configuration flexibility

The SafeXcel IP MD5/SHA Accelerator is available in a wide range of configurations that enable use in different applications and achieving different design goals, such as performance, gate count, and target cost. Any combination of the individual hash algorithms is available as a separate configuration.

The table below provides information on a subset of the available configurations. Please contact SafeNet for more information on the other configurations.

SafeXcel IP MD5/SHA Accelerator Configurations

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NAME	CONFIGURATION	MAX CLOCK FREQUENCY1	THROUGHPUT		APPROXIMATE ENGINE GATE COUNT AT 150 MHz CLOCK FREQUENCY
			AT ANY CLOCK FRENQUENCY (In bits/cycle)	AT MAX CLOCK FRENQUENCY
EIP-57a	MD5	250 MHz	7.8	1864 Mbit/s	20 kGates
EIP-57b	SHA-1	366 MHz	6.3	2362 Mbit/s	19 kGates
EIP-57c	SHA-256	333 MHz	7.8	2000 Mbit/s	23 kGates
EIP-57cl	SHA-256, low-latency	150 MHz	15.5	2592 Mbit/s	31 kGates
EIP-57ds	MD5/SHA-1, shared data path	250 MHz	7.8 (MD5) 6.3 (SHA-1)	1816 Mbit/s 1452 Mbit/s	23 kGates @ 250 MHz
EIP-57g	MD5/SHA-1/SHA-256	250 MHz	7.8 (MD5) 6.3 (SHA-1) 7.8 (SHA-256)	1864 Mbit/s 1491 Mbit/s 1864 Mbit/s	33 kGates
EIP-57h	SHA-384/SHA-512	285 MHz	12.6	3602 Mbit/s	49 kGates
EIP-57i	MD5/SHA-1/ SHA-224/SHA-256/ SHA-384/SHA-512	250 MHz	7.8 (MD5) 6.3 (SHA-1) 7.8 (SHA-224/256) 12.6 (SHA-384/512)	1970 Mbit/s (MD5) 1580 Mbit/s (SHA-1) 1970 Mbit/s (SHA-224/256) 3160 Mbit/s (SHA-384/515)	65 kGates

1 Technology and synthesis dependent; based on the use of a basic design compiler and a 0.13 mm technology.

Benefits

• Complete HW/SW solution
• High-speed hash calculation solution
• Silicon-proven implementation
• Fast and easy to integrate into SoCs
• Flexible layered design
• Complete range of configurations
• Includes data scheduling logic (message expansion)
• World-class technical support

Features

• Supported algorithms: any combination of MD5, SHA-1, SHA-224, SHA-256, SHA-384, and SHA-512
• Supports message padding
• Supports hash context switching
• Supports message sizes up to 264–1 bits
• Fully synchronous design

Deliverables

• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation script
• Synthesis script
• User’s Manual with technical specifications, including the programmer’s interface
• Developer’s Manual with step-by-step descriptions that allows developers to easily install, verify, and synthesize the design